| When I mention about electronic design automation | | | | the synthesis tool into few gates. Synthesis tool is |
| (EDA) a lot of people mistakenly think it is related to | | | | one of the examples of EDA tool. |
| electronic component manufacturing automation | | | | Even before a design using HDL is processed by a |
| which covers thing such as computer controlled of | | | | synthesis tool, there are other EDA tools that can be |
| conveyor belt and PLC programming. In fact the two | | | | used by the designers to check if their HDL codes |
| are very different in nature. | | | | follow certain rules and guidelines. These EDA tools |
| EDA domain is purely in software. It is how software | | | | are called rule checker software. The HDL design is |
| are used to help integrated circuit (IC) designers to | | | | check again good circuit design guideline in order to |
| design ICs. These software are referred to as EDA | | | | catch possible error which can caused circuit failure |
| tools. | | | | when it is converted into gates. |
| While the high level stage of the IC design requires a | | | | Network of connected gates which are synthesized |
| lot of creativity, but the low level and details part of | | | | are called netlist.There are various verification EDA |
| IC design can be very repetitive, tedious and boring. | | | | tools can be used to analyze a netlist. The tools can |
| The EDA tools help the designers in doing the | | | | be a static tools which can look at a netlist and |
| repetitive and tedious tasks. | | | | resolve it functionality mathematically. There are also |
| While in collage, students majoring in electronics learn | | | | dynamic tools such as simulators which look at how |
| basic electronic system design using small number of | | | | the circuit behave virtually when it is operating. |
| components called gates. Basic system can be | | | | Simulated input voltages and currents are fed into |
| construct with less than 10 gates. By their final year, | | | | the netlist, and the simulated output is shown to the |
| the students will learn how to construct larger | | | | designer. |
| system which consists of up to hundreds of gates. | | | | Using these verification tools, designers can verify |
| This is not how it is done in the real world. | | | | that their design work - at least in controlled |
| In the real world, a system such as the Intel Pentium | | | | simulated environment. Final verification of the actual |
| 4 chip is constructed from 14 million gates. And with | | | | chip is still needed because the long and intricate |
| the current trend, it will not be long before we pass | | | | manufacturing process can cause problem to a circuit |
| the one billion gates (in one chip) mark. This is so | | | | which not counted in during a simulated verification. |
| much different from what is thought in college. That | | | | Using various EDA tools,such as synthesis tools,rule |
| is why in the real world, IC is design using different | | | | checkers and verification tools today designers have |
| method. | | | | been able to create a chip which contains multi million |
| On the very high level a system can be described | | | | gates in it. Other than synthesis, there are also other |
| using special languages, called hardware description | | | | EDA tools that help designers with other process of |
| language (HDL). Two most prominent HDLs are | | | | an IC design such as layout tools, and timing |
| Verilog and VHDL. Verilog is widely used by designers | | | | verification tools. |
| in North America, and VHDL is widely by the | | | | The trend is to move into high abstraction using |
| european designers. | | | | higher level language, which is more abstract than the |
| Instead of designing a system on gates level, using | | | | HDLs such as C or C++ programming languages and |
| these languages a system is described at a higher | | | | let the software to do more and more task in |
| level. Then a software is used to translate this high | | | | generating the gates. Enabling of the use of C or |
| level description into gates level. This process is called | | | | C++ in designing a hardware system is done with the |
| synthesis, and the software is referred to as a | | | | goal that it will convert some of the software |
| synthesis tool. One line in HDL can be translated by | | | | engineers become hardware designers. |